Application of Evolutionary Technique for Mapping onto Network on Chip

Network on Chip (NoC) is a communication subsystem between various IPs interconnected through an on-chip router inside a single chip. The on-chip interconnection infrastructure connects the different intellectual property (IP) with the help of various industry-standard high-performance (HPC) interconnection topologies. Also, the on-chip interconnection network facilitates the connection of more Processing Elements (PE) to enable deadlock-free scheduling and parallel processing. The present work addresses one important aspect of NoC which is “Optimal Mapping” which allows the participation of cores in an optimal way for achieving low bandwidth requirement, low latency hence greater throughput. To achieve the optical mapping, a Genetic Algorithm is proposed here for the optimization of NoC performance by employing 2D Mesh topology. The genetic algorithm produces consistent and comparable results at par with standard algorithms. A deterministic seeding and successive seeding would yield better results and consume less CPU time. The proposed result is marginally better than NMAP and PSMAP.