Multi-level Programming on Radiation-Hard 1T1R Memristive Devices for In-Memory Computing
2023 14th Spanish Conference on Electron Devices (CDE)(2023)
Abstract
This work presents a quasi-static electrical characterization of 1-transistor-1-resistor memristive structures designed following hardness-by-design techniques integrated in the CMOS fabrication process to assure multi-level capabilities in harsh radiation environments. Modulating the gate voltage of the enclosed layout transistor connected in series with the memristive device, it was possible to achieve excellent switching capabilities from a single high resistance state to a total of eight different low resistance states (more than 3 bits). Thus, the fabricated devices are suitable for their integration in larger in-memory computing systems and in multi-level memory applications.
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Key words
radiation-hard,hardness-by-design,memristive devices,Enclosed Layout Transistor,in-memory computing
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