FPGA Implementation Mix Column for BCF Algorithm

Block Cipher Four Algorithm is used to protect data. BCF Architecture has been developed, but MixColoumn operation in that architecture become bottleneck. In this paper, we proposed fast MixColoumn architecture using parallel computing technique. Fast MixColoumn architecture can reduce 128 bit Encryption opereation clock from 182 to 122 clock. As a trade off, the number of Logic Elements and Registers required by the Fast MixColumn Architecture is 1.16 and 1.68 more. The Fast MixColoumn architecture offers a maximum speed of 1.15 times faster.