Simplifying RTL design and verification in chip manufacturing: A paradigm for Electronics Teaching using Open-Source tools

Jose-Miguel Galeas-Merchan,Jose-Borja Castillo-Sanchez,Martin Gonzalez-Garcia

2023 38TH CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS, DCIS（2023）

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摘要

This document introduces a wide-spreading project that allows engineering students to design, simulate, verify and manufacture a custom RTL design using HDL languages alongside a RISC-V core. To solve the deficiencies regarding functional core verification that this project features, this paper proposes the adoption of UVM and Python-based verification tools.

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关键词

RTL design,simulation,chip manufacturing,Python,Verilog,electronics teaching

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