A Design of BNN Accelerator using Gate-level Pipelined Self-Synchronous Circuit.

The energy-efficient high-throughput implementation of neural network inference is crucial in machine learning applications in the cloud and mobile end devices. Recently, remarkable progress has been made in Binary Neural Networks (BNNs) since they can be easily implemented and embedded on tiny restricted devices, saving significant storage, computation cost, and energy consumption. However, most of the BNN implementations are based on synchronous logic families with clock networks that limit the potential throughput efficiency. In contrast, asynchronous circuits have the main potential advantages of low power consumption, high-performance speed, and no clock distribution problems making it an efficient alternate implementation approach. In this work, we have applied a type of asynchronous design method, namely self-synchronous design, to the BNN model and achieved higher throughput than some of the reported works in the literature.