VLSI Implementation of RISC-V MCU with a variable stage pipeline.

Based on the RISC-V RV32IM instruction set architecture and the variable-length pipeline architecture design, we researched how to reduce the execution time of instructions. An in-order dispatch, out-of-order writeback" dispatch strategy was adopted to increase the performance of the microcontroller unit (MCU). Since the execution time of each instruction in the MCU is not the same, using a general five-layer pipeline for the design results in an excessively long execution time due to the long instructions. Therefore, we proposed a variable-length pipeline architecture based on the Hummingbird E200 architecture so that the MCU can use different pipeline lengths when executing different instructions. Due to the dispatch mechanism designed by the proposed pipeline architecture, it was not necessary to execute the instructions at the pipeline stages unrelated to their functions, thereby speeding up the completion of the instructions. When designing the pipeline architecture, we focused on the "multiplication/division" operation to execute in the execution stage of the MCU and cut the pipeline to shorten the execution time of the pipeline stage. The proposed MCU adopted an out-of-order write-back method so that instructions without data dependencies could be written back in sequence without waiting for each other, further improving system performance. The TSMC’s 0.18 μm process was used to implement this chip with the "pipeline" and "out-of-order writeback" architecture proposed in this research. Its operating clock was 120 MHz. In the same 0.18 μm process, the Hummingbird E200’s operating clock was 50MHz.