Nonlinear Capacitance Compensation Technique in a Linearity-Enhanced and Broadband GaN PA MMIC for Ku-/K-Band Applications

This article reports on exploiting a nonlinear capacitance compensation technique to achieve high linearity for power amplifier (PA) designs in III-V semiconductor technologies. High linearity is achieved by implementing multiple transistors with deliberate sizes and biasing to compensate for each nonlinear input capacitance behavior. Therefore, the composed PA core acts as one large device where each subdevice is biased individually. Moreover, this approach proves to be a reliable and easy way to improve PA linearity in III-V semiconductor technologies. The viability of this compensation is demonstrated by comparing it to other analog linearity improvement techniques such as derivative superposition. As a proof-of-concept prototype, a 17.2–20.2-GHz class-AB PA is designed in a space-evaluated 150-nm gallium nitride (GaN)-on-silicon carbide (SiC) process. Its capabilities are validated for various modulation bandwidths up to 500 MHz at several frequencies while delivering 32 dBm of output power. The measured third-order intermodulation distortion (IMD ₃ ) and the fifth-order intermodulation distortion (IMD ₅ ) are improved by 18 and 25 dB, respectively, compared to a class-AB design. The measured amplitude-to-phase (AM-PM) distortion of less than 0.07° is obtained over the entire bandwidth. Finally, noise-to-power ratio (NPR) results prove the linearity enhancement concept with values better than 15 dB up to maximum $P_{\mathrm{ out}}$ . All the results were measured without any applied digital predistortion (DPD).