Low-temperature deuterium annealing for improved electrical characteristics of SONOS

Deuterium annealing is a promising process technology for CMOS fabrication. Deuterium annealing effectively passivates interface traps at the Si-SiO2 interface, allowing for improvements in the electrical characteristics and reliability of CMOS. However, conventional deuterium annealing is typically performed at high temperatures above 400 degrees C, which can lead to unwanted dopant deactivation, random dopant fluctuation (RDF), and thermal induced stress in the backend-of-the-line (BEOL). In this study, we demonstrate the use of deuterium annealing at low temperatures, resulting in improvements in SONOS devices. Device characterizations based on subthreshold swing (SS), on-state current (ION), off-state current (IOFF), and gate leakage current (IG), as well as time-of-flight secondary ion mass spectrometry (ToF-SIMS) are included to clarify the effects of annealing.