Low Voltage Schmitt Trigger Full Adders Design for High Noise Immunity

In this paper three full adders with high noise immunity, designed using three variants of Schmitt trigger (ST) are proposed. The three variants of ST adders are based on conventional ST, dynamic threshold MOS (DTMOS) ST and variable threshold CMOS (VTCMOS) ST. The performances of the proposed ST adders are measured in terms of the hysteresis width, delay, dynamic power and ${I}_{{ON}} /{{I}} _{{OFF}}$ ratio in LT spice simulator using 45 nm PTM technology parameters. It is found that the SUM and CARRY of VTCMOS ST adder has the largest hysteresis width thus providing high noise immunity. It is also confirmed through corner analysis. The SUM and CARRY of DTMOS ST adder provides the highest ${\mathrm{I}}_{{ON}}/{I} _{{OFF}}$ ratio among all adders. It is also true for SUM of DTMOS ST for fast, typical and slow corner analysis. It is also observed that CMOS adder consumes the lowest dynamic power consumption with zero hysteresis width while VTCMOS ST adder lowers dynamic power dissipation then DTMOS ST adder. Hence the VTMOS ST adder is suitable for improved noised immunity and low voltage applications.