A Mismatch Error Calibration Method for 14-bit 500MS/s Time-interleaved Charge-Domain ADC
2022 7th International Conference on Integrated Circuits and Microsystems (ICICM)（2022）
Abstract
A mix-signal type high precision mismatch error calibration method for time-interleaved ADCs is proposed. The calibration method calibrates the clock skew mismatch error based on binary search algorithm. Based on the proposed calibration method, a 14-bit 500MS/s ADC is designed and realized in a 1P6M 0.18 $\mu$m CMOS process. Test results show the 14-bit 500MS/s ADC achieves the SNR of 69.8dBFS and the SFDR of 82.3dB, with 72.1MHz input at 500MS/s, while consumes the power consumption of 365mW.
MoreTranslated text
Key words
time-interleaved analog-to-digital converter,charge-domain,for-ground calibration,low power,mismatch error
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined