Low-Capacitance Solid-State Transformer Control Using an Analytic Filter

In the modular three-stage solid-state transformer (SST), each phase is integrated with large dc-link capacitors as energy buffers, to filter the second harmonic capacitor voltage ripple generated due to single-phase power processing. Although large dc-link capacitors reduce the coupling between stages of the SST and simplify the controller design, they compromise the reliability, safety and power density of the SST. Accordingly, a low-capacitance SST is desirable to address these challenges. To provide a high-bandwidth control for the low-capacitance SST, this paper proposes using an analytic filtering scheme rather than the low-pass filters used in conventional SST control schemes. A portion of the second harmonic power ripple in the high-voltage dc-link capacitors is processed by the SST s dc-dc stage to facilitate the use of low capacitance. The effectiveness of the proposed control is demonstrated through a simulation study in PLECS.