Quantitative Transient Synchronization Stability Margin Analysis of PLL-Based VSC Considering LVRT Control Strategy

Transient synchronization stability (TSS) issue of voltage source converter (VSC) with phase-locked-loop (PLL) has drawn great attention lately. In which, the low-voltage-ride-through (LVRT) control strategy typically characterized by the K-factor turns out to have a significant impact on both its static and dynamic behavior, while a quantitative evaluation considering both aspects has not been adequately discussed. To this end, this paper firstly establishes the feasible region of the K-factor for parametric impact analysis of the existence of equilibrium, e.g., impact of grid voltage drop and short circuit ratio (SCR). Further, a macro-quantitative evaluation of the TSS margin is achieved by using the area of region of attraction (A-ROA), then more delicate TSS margin analysis under LVRT is fulfilled by using the critical clearing time (CCT). Finally, main results of this paper are verified by MATLAB/Simulink simulations.