Design of an 8-Channel 12Bits 1MSPS SAR ADC

In this paper, an 8-channel 12-bit IMSPS single-ended SAR ADC (Successive Approximation Register Analog Digital Converter) was implemented in a standard 55nm CMOS technology. Bottom plate sampling and bootstrap switch is adopted to remove distortion in single-ended structure. A segmented DAC array with a unit value bridge capacitor is used to reduce the size of capacitor array and avoid the problem caused by fractional capacitor. A two-stages comparator was used to reduce noise and save power. The core of this SAR ADC consumes 0. 63mW power and the active area is only $0.1mm^{2}$ while achieving 11.42 bits ENOB at IMSPS sampling rates.