A Multi-Layer Stacked 3-D SRAM System Based on Wireless Transceiver using Inductively Coupled Interface in 22-NM CMOS

This paper proposes a three-dimensional SRAM system based on inductively coupled technology. The data, clock, and energy signals are delivered simultaneously through the multi-layer of the stacked chip via inductive coupling interface. By using the 22nm CMOS process, it supports the stacking of up to five layers of a chip with $25 \mu m$ in thickness for each. Simulation results show the proposed 3-D SRAM system achieves a maximum data rate of 1Gb/s while dissipating around $400 \mu W$ for memory read/write from a 0.9V power supply. The Bit Error Rate (BER) is less than $10^{-14}$ and the energy delivery efficiency is larger than 10% within the distance of 100um.