Logic Circuit Simulation based on Semi-Tensor Product

Simulation of logic circuits is a critical part of logic synthesis and verification, as it reduces the amount of time needed for various computations. However, it has been found to be difficult to simulate k-input lookup table (k-LUT) networks. This paper proposes a k-LUT logic circuit simulation method based on semi-tensor products (STPs) of matrices, which supports simulation of all nodes or only primary outputs (POs). By improving the computational efficiency of STP of matrices, the matrix encoding algorithm can accelerate all-nodes simulation. For only-PO simulation, we can run faster by partitioning the circuit based on multiple fan-out nodes. Experimental results on EPFL benchmark suites indicate that we were able to improve CPU time by 4.0x(4.8x maximum) and 7.4x (16.6x maximum) when we simulate all nodes and only POs, respectively.