SPICE Modeling and Simulation of High-Performance Wafer-Scale MoS2 Transistors

2019 IEEE 13th International Conference on ASIC (ASICON)(2019)

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摘要
This paper presents a SPICE model for two-dimensional (2D) layered materials (MoS 2 ) field-effect transistors (FETs) based on mobility calibration. We simulated the output characteristics of two different types of Mos 2 devices, single-layer (1L) and multilayer (ML) MoS 2 devices, based on this model. The excellent agreement between experimental data and simulation results verified the accuracy of the model. In order to further verify the reliability of the model, we also designed a rationed logic inverter based on ML MoS 2 device and simulated its voltage transfer characteristics (VTC), Simulation results matched well with the experimental results.
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关键词
voltage transfer characteristics,SPICE model,two-dimensional layered materials,mobility calibration,high-performance wafer-scale MoS2 transistors,rationed logic inverter,MoS2
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