Ultra Low-Power Rail-to-Rail Voltage Comparator in 65 nm CMOS Technology

The paper addresses a re-design and parameter analysis of a current-mode rail-to-rail voltage comparator with power consumption in nano-watt range across all PVT corners. The comparator design was done in general-purpose 65 nm CMOS technology with the nominal power supply voltage of 1.2 V. The circuit design needs to function properly in industrial temperature range, which is from -20°C to 85°C. The rail-to-rail input voltage range is achieved without employing two differential pairs and also without an internal voltage biasing circuitry. Furthermore, the design process can be easily automated by means of calculation spreadsheet and employing $g_{m}/I_{D}$ design methodology. The presented comparator has been analyzed for robustness and accuracy across all PVT corners using post-layout extracted netlist. A number of parameters was investigated by Monte-Carlo analysis. The power consumption does not exceed $\mathbf{1}\ \mu \mathbf{W}$ in the worst-case scenario, however in typical conditions, it remains below the first third of nano-watt range. The circuit also contains enable signal to minimize the power consumption when the circuit's function is not required. The topology itself, exhibits a promising potential for further research, since it can also work in ultra low-voltage regime thanks to only two stacked transistors.