Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology

Yusung Kim,Clifford Ong,Anandkumar Mahadevan Pillai,Harish Jagadeesh,Gwanghyeon Baek,Iqbal Rajwani,Zheng Guo,Eric Karl

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）

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摘要

An energy-efficient high bandwidth array design using 0.0300-μm ² high performance SRAM bitcell on Intel 4 CMOS technology is presented. By employing a unique combination of design techniques, the proposed 6T SRAM array design demonstrates >80% access energy improvement over a conventional 4-way interleaved 6T SRAM array design and 30% macro density improvement compared to a hierarchical 8T SRAM design for high bandwidth memory applications.

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关键词

design techniques,4-way interleaved 6T SRAM array design,hierarchical 8T SRAM design,high bandwidth memory applications,energy-efficient high bandwidth 6T SRAM design,Intel 4 CMOS technology,energy-efficient high bandwidth array design,high performance SRAM bitcell,access energy improvement,macro density improvement

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