A flash memory controller for 15μs ultra-low-latency SSD using high-speed 3D NAND flash with 3μs read time

2018 IEEE International Solid-State Circuits Conference - (ISSCC)(2018)

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摘要
In a memory hierarchy, there are various classes of memory systems depending on the access latency. A typical memory hierarchy consists of a CPU cache, DRAM, and an SSD or HDD. The DRAM has an access latency of 100ns, while flash memory has a latency of about 50μs [1]. Recently, new non-volatile memories with latencies of less than 10μs, including PRAM, MRAM, and ReRAM [2], are getting attention for business-critical systems such as big-data analysis and storage caches. To meet the low latency requirements, a new type of NAND flash, Z-NAND, with a read time (t R ) of 3μs has also been introduced [3]. Figure 20.2.1 shows a feature comparison between Z-NAND and conventional 3D NAND [4,5]. The Z-NAND achieves a read time of 3μs, which is 15–20 times faster than conventional NAND. Write throughput reaches up to 160MB/s with a 100μs program time. To further minimize read latency, I/O circuit support a DDR interface for both x8 and x16 mode. To take full advantage of such low-latency memory devices, reduction of memory access overhead is necessary. In this paper, we introduce an NVMe SSD controller which leverages the advantages of the low-latency NAND and enables the reduction of total memory access time, thereby minimizing overall system latency.
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关键词
CPU cache,DRAM,nonvolatile memories,business-critical systems,storage caches,low latency requirements,Z-NAND,conventional NAND,low-latency memory devices,memory access overhead,NVMe SSD controller,total memory access time,flash memory controller,memory systems,memory hierarchy,ReRAM,Big-data analysis,ultra-low-latency SSD,high-speed 3D NAND flash,access latency,HDD,PRAM,MRAM,read latency minimization,I/O circuit,DDR interface,time 100.0 ns,byte rate 160.0 MByte/s,time 15 mus,time 3 mus,CPU
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