13.7 A 0.23mm2 digital power amplifier with hybrid time/amplitude control achieving 22.5dBm at 28% PAE for 802.11g

2017 IEEE International Solid-State Circuits Conference (ISSCC)(2017)

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摘要
Integration of digital RF transmitters and digital power amplifiers (DPA) is becoming of great interest for systems-on-chip (SoCs) available in nanometer technologies [1]. Small and high-speed switching devices directly benefit switching power amplifiers in achieving peak power with high peak efficiency. However PA back-off efficiency remains a big challenge in high-data-rate systems with large peak-to-average ratio (PAR) such as in WLAN. Different solutions have been published to enhance power backoff efficiency but at a cost of higher complexity and larger area [2,3].
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关键词
digital power amplifier,hybrid time-amplitude control,PAE,digital RF transmitters,DPA,systems-on-chip,SoC,nanometer technology,high-speed switching devices,switching power amplifiers,peak efficiency,PA back-off efficiency,high-data-rate systems,peak-to-average ratio,WLAN,power backoff efficiency
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