30.1 A 176-Stacked 512gb 3b/cell 3D-NAND Flash with 10.8gb/mm2 Density with a Peripheral Circuit under Cell Array Architecture

Jae-Woo Park,Doogon Kim,Sunghwa Ok, Jaebeom Park,Taeheui Kwon,Hyunsoo Lee, Sungmook Lim, Sun-Young Jung,Hyeongjin Choi,Taikyu Kang,Gwan Park,Chul-Woo Yang,Jeong-Gil Choi,Gwihan Ko,Jaehyeon Shin,Ingon Yang,Junghoon Nam,Hyeokchan Sohn, Seok-In Hong,Yohan Jeong,Sung-Wook Choi,Changwoon Choi, Hyun-Soo Shin,Junyoun Lim,Dongkyu Youn,Sanghyuk Nam,Juyeab Lee,Myungkyu Ahn, Hoseok Lee,Seungpil Lee,Jongmin Park,Kichang Gwon,Woopyo Jeong,Jungdal Choi,Jinkook Kim,Kyo-Won Jin

2021 IEEE International Solid-State Circuits Conference (ISSCC)（2021）

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关键词

2D planar NAND,stacked word-lines,96-stacked-WL,cell array structure,WL stack,3D-NAND flash,storage capacity,high-density storage,peripheral circuit under cell array structure,PUC structure,rising WL-channel capacitance,RC delay,plug critical dimension,12-stage page buffer,cache connection bus,variable stage,half-plane activation,unselected string boosting scheme,adaptive WL overdrive,storage capacity 512 Gbit,PB

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