18.2 A 128Gb/s 1.95pJ/b D-Band Receiver with Integrated PLL and ADC in 22nm FinFET

Recent work has shown the ability of mm-wave (30 to 100GHz) and sub- THz (100 to 300GHz) receivers to support large bandwidths needed to meet growing data-rate demands in a variety of applications, from dielectric waveguide [1] to wireless [2], [3] links. Unfortunately, prior art either excludes the integration of critical receiver blocks (e.g. PLL, ADC) or contains complete but power-hungry LO generation [2]. A critical challenge in demonstrating sub-THz receivers with an integrated ADC is the limited availability of process nodes that provide efficient performance for both RF and mixed-signal/digital circuits simultaneously. This work presents a D-band (140GHz) receiver (RX) which integrates the RX front-end (RXFE) with PLL and ADC in a 22nm FinFET process co-optimized for RF and digital performance. The RX achieves a maximum data-rate of 128Gb/s with a total efficiency of 1.95pJ/b.