Geometry Dependent Multi-stage Compact Thermal Model for Advanced Nanosheet FETs

Gate-All-Around Nanosheet FETs (NSFETs) are promising candidates for sub 5nm node, however, the aggressive scaling NSFETs are susceptible to the self-heating effect (SHE). A precise thermal model compatible with industry SPICE model, e.g. BSIMCMG, is critical to improve the yield of NSFET-based integrated circuit design and to reduce the development timeline of the advanced process. In this paper, we propose a geometry dependent multi-stage thermal RC network to accurately predict self-heating over a wide frequency range, from DC to THz, for the advanced NSFETs, which is validated by the transient thermal simulations based on 3-D Finite Element Modeling (FEM) method. The proposed compact thermal model enables to take the impacts of nanosheet width, number of stacks (gate fingers) and gate length into account, where the stage and model parameters of the thermal RC model are determined by Bayesian deconvolution and Particle Swarm Optimization (PSO) methods, respectively. The underlying physical understandings behind the geometry dependent thermal behaviors are discussed in detail.