Optimization of Redundant Logical Units in RTL Logic Synthesis

This paper presents an optimization method for redundant arithmetic logic units in register transfer level (RTL) logic synthesis. An important existing optimization technique for redundant logic units is to merge the same logic units in the circuit, but this method depends very much on specific conditions. Once there are unmet conditions, it cannot be merged, resulting in some waste of work. Therefore, we propose a new optimization method for another possible problem - mutually exclusive logic blocks in the circuit, which can be combined with the existing merging technology to form a more systematic optimization method. Moreover, we have proved through experiments that this method can indeed optimize the circuit to a great extent.