A Reconfigurable 2D-Mesh NoC Design with Agile Development Technique of SpinalHDL

With the development of various application fields, such as automation control, medical technology, and artificial intelligence, the computation complexity and data amount increase significantly, which requires more powerful computing ability of hardware. To this end, both different domain-specific architectures (e.g. TPU) and some typically spatial architectures (e.g. GPU) have integrated more hardware resources to meet the urgent computation demands, bringing huge technique challenges on design scalability. Compared with centralized communication bus protocols (e.g. AMBA Bus), Network-on-Chip (NoC) technique has been widely used in industrial and academic large-scale architecture designs due to the lower latency, higher scalability, and higher bandwidth. Therefore, this paper focuses on parameterized 2D-meshed NOC designs that can support different network sizes, different packet widths, and several routing algorithms. To improve the coding efficiency and reusability, an emerging hardware design language of SpinalHDL embedded in Scala (one high-level language) has been adopted to develop our proposed NoC design. Finally, We measured the area and power consumption of the NoC in different configurations. For example, for a NoC with a size of 16X16, when the data bit width is 64bit and the address bit width is 20bit, the power consumption is 9mW and the area is 64963.5µm ² .