Optimization of Multiplexer Combination in RTL Logic Synthesis

The paper presents an optimizable multiplexer combination in logic synthesis of RTL level circuits. There are often some redundant multiplexers in the circuit, the deletion or optimization of these multiplexers does not affect the design behavior of circuits. Therefore, we propose a special multiplexer combination. It can be optimized on the premise that the logic function of the circuit remains unchanged, and it can also be merged with other traditional optimizable multiplexers to further optimize the circuit. In the paper, we use examples to optimize and verify, the results show that the optimizable combination can effectively reduce the number of multiplexers, The results show that the optimizable combination can significantly reduce the number of multiplexer elements, and appears more frequently and probably in the circuit. The optimizable combination is feasible and practical in the logic synthesis of circuits, which can effectively reduce the number of elements and design scale of the circuit.