Parametric design of asynchronous SAR ADC with redundancy

The successive approximation register (SAR) ADC is particularly suitable for modern technology and low power consumption due to its simple analog structure. By adding redundancy, SARADC can gain digital error correction capability to rectify the mismatch of capacitance arrays. SARADC chips typically possess specific precision and technology. SARADC can be coded to adjust the precision and technology, and generate the layout automatically, based on TED Electronic Design (TED). This paper presents a parametric SARADC generator capable of producing asynchronous SARADCs with redundancy in different processes, ranging from 5 to 10 bits.