A Novel Low Loss Lateral Planar-gate Carrier Stored IGBT with Self-biased P-type Shielding Layer

A novel low loss lateral planar-gate carrier stored (CS) IGBT with self-biased P-type shielding layer (SPS-LIGBT) is proposed and studied in this paper. The proposed structure features an emitter-connected trench near the P-type base (P-base) region, and a self-biased P-type shielding layer (PS) is placed around the CS layer. The P-base region, the CS layer, the PS layer together with the emitter-trench form a self-biased P-type channel Metal-Oxide-Semiconductor field-effect transistor (PMOS). Thanks to the PS layer, the negative impact of the CS layer on the breakdown voltage (BV) is shielded, thus the doping concentration of the CS layer ($N_{\rm{cs}}$) can be further increased without damaging the BV. When the SPS-LIGBT turns on, the potential of the self-biased PS layer is so low that the PMOS is turned off. And the holes in the drift region does not flow to the emitter through the PMOS, which enhances the conductivity modulation effect in the drift region and reduces the VCEON. When the SPS-LIGBT turns off, the potential of the self-biased PS layer rises and the PMOS is turned on. The PMOS provides an extraction path for the holes in the drift region near the trench, which reduces the turn-off loss (E OFF ). Simulation results show that the VCEON at the collector-emitter current density (JCE) of 200A/$\mathrm{cm}^{2}$ for the proposed SPS-LIGBT is only 1.11V, which is reduced by 11.9% compared with that of the LIGBT with the CS layer (CS-LIGBT). When the bus voltage (VDD) used by both devices in the turn-off test circuit is 100V, at the same VCEON of 1.18V, compared with the CS-LIGBT, the $E_{\mathrm{OFF}}$ of the SPS-LIGBT is decreased by 62.3%.