Construction and Performance Evaluation of QC-LDPC Codes With Low Error Floor

In the paper, we propose a novel construction method for quasi-cyclic (QC) low-density parity-check (LDPC) codes with lower error floor. This approach aims at eliminating the most harmful substructures by choosing proper shift values for cyclic permutation matrices (CPM). To search these harmful substructures, we introduce a high-efficiency searching algorithm, based on cycle combination and leaf cutting. In addition, a high throughput decoding platform based on multi-core CPU with SIMD instruction sets are implemented and utilized to reach the error floors of different LDPC codes efficiently. Simulation results show that for given base matrices, our method can achieve excellent performance in the high SNR region.