Exploring Efficient Implementation of Delay-based PUF Design on FPGA

The Internet of Things (IoT) presents unique challenges for security due to resource limitations. Physically unclonable function (PUF) technology offers a promising solution for cost-effective hardware identification and authentication. PUFs leverage process variations in integrated circuits to produce unique and unreplicable responses. They generate a significant number of challenge-response pairs (CRPs) for authentication. In IoT applications, Arbiter PUF (APUF) and its variants are considered the most appropriate lightweight security primitives. However, implementing a high-quality version of APUF on Field Programmable Gate Arrays (FPGA) has been challenging. This work proposes a practical implementation of APUF and XOR PUF on FPGA, improving flexibility and simplifying implementation. Our experimental analysis shows that APUF and XOR PUF demonstrate a remarkable reliability rate of 98%. Additionally, the distribution of 1s and 0s in the response bit is almost uniform, indicating a randomness of 46.81%. Furthermore, we conduct machine learning modeling attacks to assess the efficacy of the APUF and XOR PUF implementation.