Pulse-Width Trigger Method in 10GSPS Data Acquisition System

In linear FM signal detection applications such as communications and radar, the pulse width of the signal can vary by hundreds of picoseconds, requiring the acquisition system to have higher acquisition performance and trigger performance to acquire and capture signals with small variations in pulse width. As one of the advanced trigger functions of a data acquisition system, pulse-width trigger has the ability to detect the pulse width of the input signal in real time and control the acquisition process in order to capture the signal that meets the conditions of pulse-width trigger. With the increasing frequency of the signal, the high-speed acquisition system is required not only to have the ability to capture small changes in the signal pulse width, but also to have a higher ability to detect the minimum pulse width. In high-speed acquisition systems, the traditional pulse-width trigger is realized by the analog pulse-width trigger. The analog pulse-width trigger has the advantage of real-time, but it also has the problem of large trigger jitter and low trigger accuracy due to the non-linear lead of the high-speed analog device and the analog-digital synchronization. This paper proposes a high-precision digital pulse-width trigger method. The method adopts the design of synchronizing the sampling data with the trigger data source, which solves the problem of trigger jitter in analog pulse-width trigger. The digital pulse-width trigger uses a method of converting high-speed parallel sampling data into parallel feature data that can characterize the edge features of the pulse signal. Then, according to the characteristics of the starting edge and the ending edge of the pulse width, the pulse width of the pulse signal is calculated. Finally, the pulse width trigger judgment is performed, and the trigger point position is obtained in real time to achieve the high-precision pulse width trigger. The method is implemented in a 10GSPS data acquisition system using an ADC+FPGA architecture. After testing, the minimum detectable pulse width of the digital pulse-width trigger is 200ps, and the pulse-width trigger jitter is less than 100ps.