A 1.5-mA 2.5-GHz LNA With Reusing On-Chip Matching Network in 55nm CMOS Technology

A 2.5-GHz 1.2-V 1.5-mA low-noise amplifier (LNA) with a minimum of 3-dB noise figure (NF) at 2.5 GHz, −15-dBm IIP3, with on-chip matching network is demonstrated. The LNA is designed to realize low noise in the premise of low power consumption. The 55nm CMOS LNA is simulated with embedded electrostatic discharge (ESD) protection diodes that add 165- and 185-fF loads at the RF input ports. The on-chip matching network offers a single-ended $50 \Omega$ RF terminal that is shared by both TX- and RX-chains through switch MOS. At 2.5 GHz, the LNA has a simulated input return loss (S11) of −13.6 dB and the transmission gain (S21) of 16.4 dB. The Noise Figure (NF) is 3 dB and the input third-order intercept point (IIP3) is −15-dBm. The LNA (excluding the buffer) occupies an area of 0.21 mm ² .