Thermal Aware Floorplan Optimization of SoC in Mobile Phone

Mobile phone functions are evolving towards high-end cameras, AI functions, and high-performance gaming environments. To implement these functions, the System on Chip (SoC) Application Processor (AP) of mobile places the system blocks with more functions in a limited space. The problem is that when thermal runaway occurs due to overlapping of heat between system blocks on chip, the performance by temperature control may be lowered. When placing the system blocks in the chip, the level of heat generation of each system is predicted and the floor-planning is arranged to have the lowest temperature during scenario operation. After analyzing the temperature map that is generated from the thermal simulation result, the location of the system block that becomes a hotspot is moved to another location. the process of waiting for the result by requesting the simulation again is repeated to determine the final temperature-optimized floorplan. In this process, there is a problem that it takes a long time while repeating the simulation after design. If the designer can check the temperature map in real time, it is possible to design in consideration of the temperature-optimized layout before the detailed design comes out. Also, it is possible to find the optimal arrangement case with the lowest temperature. This paper explains a method to calculate the temperature distribution within the chip in real-time according to the floorplan arrangement in the initial stage of chip design. A method of reducing the time to make the thermal resistance matrix and describes the optimize method to find the lower optimal arrangement.