A 3.0 Gb/s/pin 4^th generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package

A 1.2 V, 3.0 Gb/s/pin 16Tb NAND flash memory package with proposed 4 ^th generation F-chip is presented. It is implemented with self-training techniques such as hybrid delay locked loop (DLL) and 3-step duty cycle correction (DCC) to overcome the speed bottlenecks in F-chip to NAND interface. Also, its multi-termination feature improves power efficiency by providing the use of different terminations on its interfaces. This work achieves an I/O speed of 3.0 Gb/s and power consumption of 58mW which are an improvement of 66% and 23.3%, respectively, in comparison with 3 ^rd generation F-chip.