A Low-Temperature SiO 2 Interfacial Layer Preparation using Rapid Thermal Oxidation Process for GAA Nanosheet Based I/O Transistor

In this paper, a low-temperature SiO 2 interfacial layer preparation using rapid thermal oxidation (RTO) process for gate-all-around (GAA) nanosheet (NS) based input-output (I/O) transistor is explored in detail. After preparing high-quality thick SiO 2 IL at 600℃, its MOS capacitor with W/TiN/HfO 2 /SiO 2 /Si substrate structure achieves well behaved multi-frequency capacitance-voltage characteristics, low leakage current, low interfacial trap density (D it ), and excellent time-dependent dielectric breakdown. For instance, its gate leakage under flatband voltage (V fb ) -1 V is only 2.48 × 10 –9 A/cm 2 , its minimum D it reaches 5.1 × 10 10 eV −1 cm −2 , and its ten-year lifetime effective voltage can reach 3.62 V at a failure rate of 0.01%. Moreover, a GAA NS based I/O device with a healthy gate stack is successfully prepared using this low-temperature SiO 2 interfacial layer and its gate leakage is below 1 × 10 –13 A, approaching the detection limit. These above results indicate that this low-temperature RTO-grown SiO 2 IL has excellent quality and can meet the requirements of GAA NSs I/O transistors.