Monolithically integrated self-aligned SiN edge coupler with <0.6/0.8 dB TE/TM insertion loss, <-39 dB back reflection and >520 mW high-power handling capability

Yusheng Bian,Takako Hirokawa, Vaishnavi Karra, Arpan Dasgupta,Won Suk Lee,Abdelsalam Aboketaf,Francis Afzal, Ryan Sporer,Karen Nummy,Ken Giewont, Nickolas C. Harris,Reza Baghdadi, Shashank Gupta, Keith Donegan,Thomas Houghton, Brian Popielarski, Kevin K. Dezfulian, Petar Ivanov Todorov,Bo Peng,Sujith Chandran,Mohamed Gheith, Ian Stobert, Mini Modh Ghosal,Jae Kyu Cho, Apoorva Vakil, Sunoo Kim,Zhuo-Jie George Wu,Andy Stricker,Kate McLean,Benjamin V Fasano,Michal Rakowski,Qidi Liu, Matt Rauer, Ryan Gallagher, Ranjani Sirdeshmukh, Norm Robson, Ian Melville,Rod Augur,Jae Gon Lee,Wenhe Lin,George Gifford,Robert Fox,Vikas Gupta,Anthony Yu, John Pellerin,Ted Letavic

2023 Optical Fiber Communications Conference and Exhibition (OFC)（2023）

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摘要

We experimentally demonstrated V-groove-based self-aligned SiN edge coupler (EC) on a monolithic CMOS-SiPh platform. <0.6/0.8 dB TE/TM SMF-EC transmission efficiency, in conjunction with <-39 dB back reflection and >520 mW power handling capability were achieved.

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关键词

high-power handling capability,monolithic CMOS-SiPh platform,monolithically integrated self-aligned SiN edge coupler,mW power handling capability,noise figure -39.0 dB,noise figure 0.6 dB,noise figure 0.8 dB,power 520.0 mW,SiN/bin,V-groove-based self

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