Effect of Power Supply Noise on Logical Reliability of MOS based Circuits

This electronic We have investigated supply noise reduction of Metal-Oxide-Semiconductor (MOS) based logic circuits both at 500 nm and 45 nm technology nodes. Logical failure of Complementary-MOS inverter with supply voltage lowering can be restricted at low package inductances. Noise reduction of 5-input combinational logic is performed by subsequently reducing number of transistors and applying dynamic logic within the design. The change of voltage level due to dynamic logic has been corrected using a proposed design where high capacitance paths from switching transistors to output reduces supply noise while maintaining logical reliability. Logic reconstruction occurs in level triggered D-flipflop with transistors reduction (18 to 10) at 45 nm technology node and package inductance as high as 1 mH. Supply noise for master-slave negedge triggered D-flipflop is found to be frequency dependent at low packages and large channel circuits. Large package and short channel contribute large noise current which makes the design almost independent of applied clock frequency.