Simulation Research on Single Event Transient Characteristics of Different Combinational Logic Cells with Nano-Scale FDSOI CMOS Process

This paper uses 3D TCAD simulation tool to study the single event transient (SET) characteristics of four types of logic cells (INVX2, NAND, NOR, INV_STACK) with nano-scale FDSOI CMOS process, and the influence of the LET value on the SET pulse width characteristics of the four cells. Simulation shows that when heavy ions strike NMOS, among the four cells, the NAND structure introduces the smallest amplitude and pulse width, while the NOR structure introduces the largest amplitude and pulse width. On the other hand, when PMOS is stricken, we got opposite results. In both cases, the INV_STACK structure has advantage in SET minimization. Based on the simulation results, it is indicated that the SET amplitude and pulse width of the four logic cells all increase with the LET value, while the increase rates decline with LET.