Characterization of a Coherent Hardware Accelerator Framework for SoCs.

Accelerators rich architectures have become the standard in today’s SoCs. After Moore’s law diminish, it is common to only dedicate a fraction of the area of the SoC to traditional cores and leave the rest of space for specialized hardware. This motivates the need for better interconnects and interfaces between accelerators and the SoC both in hardware and software. Recent proposals from industry have put the focus on coherent interconnects for big external accelerators. However, there are still many cases where accelerators benefit from being directly connected to the memory hierarchy of the CPU inside the same chip. In this work, we demonstrate the usability of these interfaces with a characterization of a framework that connects accelerators that benefit from having coherent access to the memory hierarchy. We have evaluated some kernels from the Machsuite benchmark suite in a FPGA environment obtaining performance and area numbers. We obtain speedups from 1.42 × up to 10 × only requiring 45k LUTs for the accelerator framework. We conclude that many accelerators can benefit from having this access to the memory hierarchy and more work is needed for a generic framework.