A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test

With the capability improvements in modern System-on-Chips (SoCs), the complexity of SoCs is increasing. Thus, manufacturers are investing heavily in designing and testing their devices. This complexity is causing a continuous expansion in the size of embedded memory structures. As a result of the shrinking dimensions of the transistors, memories are increasingly susceptible to Multiple Bit Upsets due to cosmic radiations. Testing memories requires more details about the internal hardware configurations. However, these details are not provided to the final customer, who is left with inexplicable effects. This paper proposes a new method to reconstruct architectural details from embedded SoC memories. This method extracts memory design parameters from Multiple Bit Upsets (MBUs) generated through a single irradiation test. The algorithm was tested on around 5,500 randomly generated memories. Each memory was injected with 100 Multiple Event Upsets (MEUs). The algorithm was set to test for each memory 20, 40, 60, 80, and 100 MEUs to validate the proposed approach. Alongside the correct memory design configuration (MDC), the algorithm found other possible MDCs. The quantity of these equivalent configurations decreased with the increment of the considered MEUs. This number decreased to an average of 2 equivalent MDCs when considering 100 MEUs.