Method for Data-Driven Pruning in Micropipeline Circuits

2023 IFIP/IEEE 31ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION, VLSI-SOC(2023)

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摘要
Asynchronous Micropipeline circuits are an effective alternative to their synchronous counterparts for reducing dynamic power consumption because they offer proper signaling for disabling useless blocks. In this paper, a novel approach is suggested that uses such signaling to prune irrelevant data. The result is a decrease in the switching activity and an increase of the average throughput, making the circuit more power efficient. The method relies on new control-path elements, which conditionally prune data-path elements. Thanks to these controllers, the registers do not sample new data when pruned and subsequent data propagation is avoided. The former are able to replace any standard controllers in Micropipeline circuits without changing the architecture of the control-path. Furthermore, the outline of the methodology is given for a Micropipeline circuit and is explained through an illustrative example.
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