A 12-bit SAR ADC with a reversible V

A low-power 12-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a reversible V CM -based capacitor (RVC) switching scheme is presented in this paper. The switching power consumption of the proposed scheme is 95% and 62.3% lower than that of conventional and V CM -based capacitor switching schemes, respectively. The use of a segmented DAC structure reduces the size of the largest capacitor from 2 11 unit capacitors in the conventional capacitor array to 2 4 unit capacitors. This 75% reduction in the capacitor area decreases the settling time of the DAC capacitor network as well as requirements on the bandwidth and driving capability of the reference source V REF . An ADC prototype with an active area of 0.218 mm 2 is fabricated in 180-nm 1P6M CMOS process. With supply of 1.8 V and sampling rate of 10 MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 58.9 dB and consumes power of 0.36 mW, yielding a figure of merit (FOM) of 59.8fJ/conversion-step.