Cycle-to-Cycle Variation Suppression in ReRAM-Based AI Accelerators

As a non-volatile memory, currently ReRAM (Resistive Random Access Memory) is emerging for the low power and high performance AI accelerator design. However, ReRAM always suffer from significant cycle-to-cycle variations, which significantly degrades the inference accuracy. In this study, we firstly fabricate ReRAM wafers and test them. Then we propose both level optimization and pulse regulation methods to mitigate the adverse impact of cycle-to-cycle variations of ReRAM, improve the inference accuracy, lower the energy consumption, and decrease the latency of the AI accelerators.