System Aware Floorplanning for Chip-Package Co-design

SoC floorplanning is crucial as it bridges the system design and the physical design of the chip. In this paper, we present a new floorplanning solution based on a novel floorplan model that more closely depicts the design challenges imposed by modern SoC system constraints. Our experimental results demonstrated that this solution is able to create floorplans with hard peripheral instances and soft rectilinear instances with zero white space while supporting system constraints on multiple design instances.