10-bit Area-reduced DAC for EIT Applications Using 180 nm Technology

This paper focuses on the implementation of a digital-to-analog converter (DAC) for Electrical Impedance Tomography (EIT) applications using 180 nm CMOS technology. Intended for use in a system with a clock of 100 MHz, and input signal frequency of 125 kHz. The 10-bit resolution DAC was built with a segmented approach, where the 6 most significant bits were assigned to a thermometer-coded matrix and the remaining 4 bits to a binary-weighted structure. Techniques for area and power reduction were used to achieve a result of 0.074 mm2 core size and 11.3 mW of power consumption, with an expected DNL of 1 LSB and INL of 1 LSB for a 2 MHz input frequency.