Voltage scheme for string-select transistors to improve inhibition characteristics during 1-bit erase in vertical NAND flash

We propose a new voltage scheme for string-select (SS) transistors to improve inhibition characteristics of unselected cells during selective 1-bit erase in vertical NAND flash memory. Different from the reported schemes, we apply different control voltages to each of the three SS transistors of unselected drain select lines and all source select lines to lower the channel potential. The change in the channel potential depending on the voltage of the SS transistors and the resulting gate-induced drain leakage is explained via TCAD simulation. The proposed pulse method can reduce the V-th of the 1-bit cell selected for erase by 168% compared to the reported method while maintaining the same inhibition characteristics.