A 20.8-23.2GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving-47.05 dBc reference spur and-245.9dB FOM in 40nm CMOS Technology

This paper presents a 20.8-23.2GHz integer-N sub-sampling phase-locked loop (SSPLL) with low-reference spur and low-phase noise. A transformer-coupled based voltage controlled oscillator (VCO) is employed and its output is feedback as the input to SSPD in sub sampling PLL to reduce the reference spur without requiring extra area and power consumption. In addition, a common source feedback circuit is adopted in the proposed sub-sampling charge pump (SSCP) to reduce current mismatch. The proposed sub-sampling PLL is implemented in a 40nm CMOS technology, measured results exhibit a frequency tuning range of 10.9% from 20.8 to 23.2GHz. The measured phase noise is 106.92@1MHz offset, the reference spur is-47.05 dBc. The typical power consumption is 29.1 mW from a 1.1V supply voltage, leading to a PLL FoM of-245.9 dB. The PLL occupies a core area of 1.2mm(2).