Signal and Power Integrity Design and Analysis for Bunch-of-Wires (BoW) Interface for Chiplet Integration on Advanced Packaging
2023 IEEE 73RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, ECTC(2023)
摘要
This work advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and joint simulation of signal and power integrity of BoW-based die-to-die interconnects with advanced packaging technology. The study covers data rates up to 16 Gbps. This paper presents a circuit-level implementation of the BoW slice that consists of a driver on one chiplet and a receiver on another chiplet. This work compares the performance of various combinations of high-density transmission lines with different line-and-space and wirelengths. It presents configurations of the BoW data lines that have extremely low power dissipation, less than 0.2 pJ/bit at 8 and 16 Gbps.
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关键词
Bunch-of-Wires, chiplet, interconnects, Power integrity, Signal integrity
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