Experimental Exploration of the Backside ESD Impacts on an IC Chip in Flip Chip Packaging

This paper presents on-chip characterization of electro-static discharge (ESD) impacts applied on the Si-substrate backside of a flip-chip mounted integrated circuit (FC-IC) chip. An FC-IC chip has an open backside and there is a threat of reliability problems and malfunc-tions caused by the backside ESD. We prepared a test FC-IC chip and measured Si-substrate voltage fluctuations on its frontside by an on-chip monitor (OCM) circuit. The voltage surges as large as 200 mV were ob-served on the frontside when a 200-V ESD gun was irradiated through a 5 k omega contact resistor on the backside of a 350 mu m thick Si substrate. The distribution of voltage heights was experimentally measured at 20 on-chip locations among thinned Si substrates up to 40 mu m, and also explained in full-system level simulation of backside ESD impacts with the equivalent models of ESD-gun operation and FC-IC chip assembly.