H-Band Power Amplifiers in 65-nm CMOS by Adopting Output Power Maximized G-Core and Transmission Line-Based Zero-Degree Power Combining Networks.

This article proposes high-gain, high-output-power, and high-power-added efficiency (PAE) power amplifiers (PAs) by adopting an output power maximized (OPM) maximum achievable gain ( $G_{\text{max}}$ )-core with the transmission line (TL)-based zero-degree power combiners (ZDCs) and zero-degree splitters (ZDSs). By utilizing the proposed small-and large-signal two-port network parameter-based analysis for implementing the $G_{\text{max}}$ -core, the last-stage OPM $G_{\text{max}}$ -core can maximize large-signal output power and small-signal gain at the same time. In addition, by adopting the $G_{\text{max}}$ -concept in all amplifying stages, the amount of gain per stage can be maximized, leading to higher PAE. For implementing the low-loss power combining (PC) and splitting networks, ZDC and ZDS are adopted. By adopting the proposed OPM $G_{\text{max}}$ -core and ZDCs and ZDSs, six-stage 250-GHz two-and four-way PC PAs are implemented in a 65-nm CMOS process. The two PAs achieve $P_{\text{sat}}$ of 9.2 and 10.5 dBm, $\text{OP}_{1\,\text{dB}}$ of 6 and 7.7 dBm, PAE of 4.6% and 2.8%, and power gains of 28 and 26 dB at 245 and 243 GHz, respectively.